This invention relates to delay measuring circuits.
The invention has a particular application to integrated circuits wherein a large number of individual cells are implemented on a single chip, the chip circuitry including such cells in the circuit implemented on the chip. Production process variation and temperature and power voltage supply fluctuations are the same for every cell on one chip. Thus, all these cells have the same characteristics, such as switching levels and propagation delay, the relative delay between individual cells being minimal. However, production process variations and temperature and power supply voltage fluctuations can cause a large absolute delay difference between two integrated circuit chips. Thus, circuit designs needing accurate absolute delays cannot generally be implemented on integrated circuit chips.
U.S. Pat. No. 4,623,805 discloses a clock signal distribution system employing a plurality of clock distribution chips responsive to a main clock signal. The system provides for the clock signal generated by each chip to be automatically adjusted to be delayed by an amount corresponding to the delay provided by an accurate fixed delay external to the chip, such as a fixed length of wire. Thus the clock signals provided by all the clock distribution chips are synchronized with one another. For this purpose, each chip includes a multitapped delay line, a phase comparator, a multiplexer having inputs connected to the delay line taps, and a counter. The phase comparator compares the phase of the output of the external fixed delay with the clock signal generated by the chip, the arrangement being such that the counter controls the multiplexer to select an appropriate tap signal output to provide a clock signal delay corresponding to the fixed, external delay.